1. Field of the Invention
The present invention relates to a multichip module including a plurality of semiconductor chips.
2. Description of Related Art
In recent years, there has been a demand for higher density integration and size reduction of a semiconductor device. To this end, a multichip module (MCM, see Japanese Unexamined Patent Publication No. 2000-188369) and a chip scale package (CSP, see Japanese Unexamined Patent Publication No. 2002-118224) have been developed which satisfy the aforesaid demand.
FIG. 8 is a schematic sectional view illustrating the construction of a prior art semiconductor device having a multichip module structure.
The semiconductor device 81 includes a wiring board 82, a semiconductor chip 83 disposed on the wiring board 82, and a semiconductor chip 84 disposed on the semiconductor chip 83. The semiconductor chips 83, 84 each include a functional element 83a, 84a formed in one surface thereof. The semiconductor chip 83 is bonded onto the wiring board 82 with its face up, i.e., the surface of the semiconductor chip 83 formed with the functional element 83a faces away from the wiring board 82. The semiconductor chip 84 is bonded onto the semiconductor chip 83 with its face up, i.e., the surface of the semiconductor chip 84 formed with the functional element 84a faces away from the semiconductor chip 83. An interlevel insulating material 86 is interposed between the semiconductor chips 83 and 84.
The semiconductor chip 83 is greater in size than the semiconductor chip 84 as seen perpendicularly to the surfaces formed with the functional elements 83a, 84a, so that the surface of the semiconductor chip 83 on which the semiconductor chip 84 is bonded has a peripheral area not opposed to the semiconductor chip 84. Electrode pads 83b connected to the functional element 83a are provided on the peripheral area of the semiconductor chip 83. Electrode pads 84b connected to the functional element 84a are provided on a peripheral area of the surface of the semiconductor chip 84 formed with the functional element 84a. 
The wiring board 82 is greater in size than the semiconductor chip 83 as seen perpendicularly to the wiring board 82, so that the surface of the wiring board 82 on which the semiconductor chip 83 is bonded has a peripheral area not opposed to the semiconductor chip 83. Electrode pads not shown are provided on the peripheral area of the wiring board 82, and connected to the electrode pads 83b, 84b via bonding wires 87, 88, respectively.
The semiconductor chips 83, 84 and the bonding wires 87, 88 are sealed in a mold resin 89.
Metal balls 85 serving as external connection members are provided on a surface of the wiring board 82 opposite from the surface on which the semiconductor chip 83 is bonded. Electrode pads (not shown) of the wiring board 82 are rewired in and on the wiring board 82 and respectively connected to the metal balls 85.
The semiconductor device 81 is connected to a second wiring board via the metal balls 85.
FIG. 9 is a schematic sectional view illustrating the construction of a prior art semiconductor device having a chip scale package structure.
The semiconductor device 91 includes a semiconductor chip 92. The semiconductor chip 92 includes a functional element 92a formed in one surface thereof, and an insulation film 93 covering the functional element 92a. The insulation film 93 has openings formed in predetermined portions thereof.
Rewiring layers 94 each having a predetermined pattern are provided on the insulation film 93. The rewiring layers 94 are connected to the functional element 92a through the openings of the insulation film 93. Columnar external connection terminals 95 project from predetermined portions of the rewiring layers 94, and metal balls 96 serving as external connection members are respectively bonded onto distal ends of the external connection terminals 95.
The insulation film 93 and the rewiring layers 94 on the surface of the semiconductor chip 92 formed with the functional element 92a are covered with a protective rein layer 97. The external connection terminals 95 each extend through the protective resin layer 97. Side surfaces of the semiconductor chip 92 are flush with side surfaces of the protective resin layer 97. With the provision of the protective resin layer 97, the semiconductor device 91 has a generally rectangular prism outer shape. Therefore, the semiconductor device 91 has substantially the same size as the semiconductor chip 92 as seen perpendicularly to the semiconductor chip 92.
The semiconductor device 91 is connected to a wiring board via the metal balls 96.
In the semiconductor device 81 of FIG. 8, however, the wiring board 82 should have a greater size than the semiconductor chip 83 to provide an area for the connection with the bonding wires 87, 88. Therefore, the semiconductor device 81 (package) is greater in size than the semiconductor chips 83, 84, particularly, as measured parallel to the wiring board 82. Accordingly, the semiconductor device 81 requires a greater mounting area on the second wiring board.
Where a lead frame is used instead of the wiring board 82 (see, for example, Japanese Unexamined Patent Publication No. 2002-9223), a similar problem occurs.
On the other hand, the semiconductor device 91 of FIG. 9 includes no wiring board. With this construction, it is impossible to incorporate a plurality of chips (semiconductor chips 92) in the semiconductor device. In order to mount a plurality of semiconductor chips 92 on a wiring board, a plurality of such semiconductor devices 91 should be arranged laterally on the wiring board, requiring a greater mounting area. In addition, the semiconductor chips 92 are connected to one another via the wiring board, so that the total wiring length is increased. This makes it difficult to increase the signal processing speed of the overall system.